Altium

Design Rule Verification Report

Date: 8/26/2022
Time: 2:51:25 PM
Elapsed Time: 00:00:01
Filename: Z:\APPLICATION\BOARDS\MEMS Adapter DIL24\QVAR\MS SW-QV 2_5x3 14L r6\MKI227AA\STEVAL-MKI227A.PcbDoc
Warnings: 0
Rule Violations: 17

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.2mm) (All),(All) 9
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.254mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.15mm) (All),(All) 8
Silk To Solder Mask (Clearance=0.14mm) (IsPad),(All) 0
Silk to Silk (Clearance=0.15mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 17

Clearance Constraint (Gap=0.2mm) (All),(All)
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-1(6.34mm,-7.875mm) on Top Layer And Pad U1-2(6.34mm,-8.375mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-10(8.66mm,-8.375mm) on Top Layer And Pad U1-11(8.66mm,-7.875mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-10(8.66mm,-8.375mm) on Top Layer And Pad U1-9(8.66mm,-8.875mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-12(8mm,-7.7mm) on Top Layer And Pad U1-13(7.5mm,-7.7mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-13(7.5mm,-7.7mm) on Top Layer And Pad U1-14(7mm,-7.7mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-2(6.34mm,-8.375mm) on Top Layer And Pad U1-3(6.34mm,-8.875mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-3(6.34mm,-8.875mm) on Top Layer And Pad U1-4(6.34mm,-9.375mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-5(7mm,-9.55mm) on Top Layer And Pad U1-6(7.5mm,-9.55mm) on Top Layer
Clearance Constraint: (0.15mm < 0.2mm) Between Pad U1-8(8.66mm,-9.375mm) on Top Layer And Pad U1-9(8.66mm,-8.875mm) on Top Layer
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Minimum Solder Mask Sliver (Gap=0.15mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.007mm < 0.15mm) Between Pad U1-1(6.34mm,-7.875mm) on Top Layer And Pad U1-14(7mm,-7.7mm) on Top Layer [Top Solder] Mask Sliver [0.007mm]
Minimum Solder Mask Sliver Constraint: (0.023mm < 0.15mm) Between Pad U1-10(8.66mm,-8.375mm) on Top Layer And Pad U1-12(8mm,-7.7mm) on Top Layer [Top Solder] Mask Sliver [0.023mm]
Minimum Solder Mask Sliver Constraint: (0.007mm < 0.15mm) Between Pad U1-11(8.66mm,-7.875mm) on Top Layer And Pad U1-12(8mm,-7.7mm) on Top Layer [Top Solder] Mask Sliver [0.007mm]
Minimum Solder Mask Sliver Constraint: (0.023mm < 0.15mm) Between Pad U1-14(7mm,-7.7mm) on Top Layer And Pad U1-2(6.34mm,-8.375mm) on Top Layer [Top Solder] Mask Sliver [0.023mm]
Minimum Solder Mask Sliver Constraint: (0.023mm < 0.15mm) Between Pad U1-3(6.34mm,-8.875mm) on Top Layer And Pad U1-5(7mm,-9.55mm) on Top Layer [Top Solder] Mask Sliver [0.023mm]
Minimum Solder Mask Sliver Constraint: (0.007mm < 0.15mm) Between Pad U1-4(6.34mm,-9.375mm) on Top Layer And Pad U1-5(7mm,-9.55mm) on Top Layer [Top Solder] Mask Sliver [0.007mm]
Minimum Solder Mask Sliver Constraint: (0.007mm < 0.15mm) Between Pad U1-7(8mm,-9.55mm) on Top Layer And Pad U1-8(8.66mm,-9.375mm) on Top Layer [Top Solder] Mask Sliver [0.007mm]
Minimum Solder Mask Sliver Constraint: (0.023mm < 0.15mm) Between Pad U1-7(8mm,-9.55mm) on Top Layer And Pad U1-9(8.66mm,-8.875mm) on Top Layer [Top Solder] Mask Sliver [0.023mm]
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